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SI9161
Vishay Siliconix
SI9161
Optimized-Efficiency Controller for RF Power Amplifier Boost Converter
FEATURES
* Si9160 architecture optimized for "light-load" efficiency * High Frequency Switching (up to 2 MHz) * Optimized Output Drive Current (300 mA) * Standby Mode * Wide Bandwidth Feedback Amplifier * Single-Cell LiIon and Three-cell NiCd or NiMH Operation
DESCRIPTION
The SI9161 Optimized-Efficiency Controller for RF Power Amplifier Boost Converter is a fixed-frequency, pulse- widthmodulated power conversion controller designed for use with the Si6801 application specific MOSFET. The SI9161 and the Si6801 are optimized for high efficiency switched-mode power conversion at 1 MHz and over. The device has an enable pin which can be used to put the converter in a low-current mode compatible with the standby mode of most cellular phones. It has a light-load pin which enables circuitry optimizing efficiency at loads typical of receive operation. A wide bandwidth feedback amplifier minimizes transient response time allowing the device to meet the instantaneous current demands of today's digital protocols. The input voltage range accommodates minimal size and cost battery pack configurations. Frequency control in switching is important to noise management techniques in RF communications. The SI9161 is easily synchronized for high efficiency power conversion at frequencies in excess of 1 MHz. Optimizing the controller and the synchronous FETs results in the highest conversion efficiency over a wide load range at the switching frequencies of interest (1 MHz or greater). It also minimizes the overshoot and gate ringing associated with drive current and gate charge mismatches. When disabled, the converter requires less than 330 A. This capability minimizes the impact of the converter on battery life when the phone is in the standby mode. Finally, operating voltage is optimized for LiIon battery operation (2.7 V to 4.5 V) and can also be used with three-cell NiCd or NiMH (3 V to 3.6 V), as well as four-cell NiCd or NiMH (4 V to 4.8 V) battery packs.
APPLICATION CIRCUIT
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ABSOLUTE MAXIMUM RATINGS
Voltages Referenced to GND. VDD, VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V Linear Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VDD +0.3 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VDD +0.3 V Peak Output Drive Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 mA Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . 150C Power Dissipation (Package)a 16-Pin TSSOP (Q Suffix)a, b . . . . . . . . . . . . . . . . . . . . . . . . . 925 mW Thermal Impedance (JA)a 16-Pin TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135C/W Notes a. Device mounted with all leads soldered or welded to PC board. b. Derate 7.4 mW/C above 25C.
Exposure to Absolute Maximum rating conditions for extended periods may affect device reliability. Stresses above Absolute Maximum rating may cause permanent damage. Functional operation at conditions other than the operating conditions specified is not implied. Only one Absolute Maximum rating should be applied at any one time.
SPECIFICATIONS
Limits Test Conditions Unless Otherwise Specifieda Parameter Reference
Output Voltage VREF IREF = -10 A TA = 25C 1.455 1.477 1.50 1.545 1.523 V B Suffix -25 to 85C LL = VDD, 2.7 V VDD, VS 6.0 V, GND = PGND
Symbol
Minb
Typ
Maxb
Unit
Oscillator
Maximum Frequencyc Oscillator Frequency Accuracy ROSC Peak Voltage Voltage Stability
c
fMAX
VDD = 5 V, COSC = 47 pF, ROSC = 5.0 k VDD = 3.0 V, fOSC = 1 MHz (nominal) COSC = 100 pF, ROSC = 7.0 k, TA = 25C
2.0 -15 1.0 15
MHz % V 8 5 115 % kHz
VROSC f/f fLL 4 V VDD 6 V, Ref to 5 V, TA = 25C Referenced to 25C LL = 0 V, COSC = 100 pf, ROSC = 7.0 k -8
Temperature Stabilityc Light-Load Frequencyc
Error Amplifier (COSC = GND, OSC Disabled)
Input Bias Current Open Loop Voltage Gain Offset Voltage Unity Gain Bandwidthc Output Current Power Supply Rejectionc IB AVOL VOS BW IOUT PSRR Source (VFB = 1 V, NI = VREF) Sink (VFB = 2 V, NI = VREF) 4 V < VDD < 6 V 0.4 VNI = VREF VNI = VREF , VFB = 1.0 V -1.0 47 -15 55 0 10 -2.0 0.8 60 -1.0 15 1.0 A dB mV MHz mA dB
UVLOSET Voltage Monitor
Under Voltage Lockout Hysteresis UVLO Input Current VUVLOHL VUVLOLH VHYS IUVLO(SET) UVLOSET High to Low UVLOSET Low to High VUVLOLH - VUVLOHL VUVLO = 0 to VDD -100 0.85 1.0 1.2 200 100 1.15 V mV nA
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SPECIFICATIONS
Limits Test Conditions Unless Otherwise Specifieda Parameter Output Drive (DR and DS)
Output High Voltage Output Low Voltage Peak Source Output Current Peak Sink Output Current Break-Before-Make VOH VOL ISOURCE ISINK tBBM VDD = 2.7 V VS = 5.3 V VDD = 2.7 V VDD = 6.0 V IOUT = -10 mA IOUT = 10 mA VS = 5.3 V VS = 5.3 V 250 5.15 5.2 0.06 -300 300 40 0.15 -250 mA ns V B Suffix -25 to 85C LL = VDD, 2.7 V VDD, VS 6.0 V, GND = PGND
Symbol
Minb
Typ
Maxb
Unit
Logic
ENABLE Delay to Output ENABLE Logic Low ENABLE Logic High ENABLE Input Current Light Load Delay to Outputc Light Load Logic Low Light Load Logic High Light Load Input Current tdEN VENL VENH IEN tdLL VLLL VLLH ILL LL = 0 to VDD 2.4 -1.0 1.0 ENABLE = 0 to VDD Light Load Falling to OUTPUTS 0.8 VDD -1.0 1.4 0.8 1.0 ENABLE Rising to OUTPUT, VDD = 6.0 V 1.4 0.2 VDD s V A s V A
Duty Cycle
Maximum Duty Cycle DMAX/SS Input Current CYCLEMAX IDMAX VDD = 6.0 V DMAX = 0 to VDD -100 80 95 100 % nA
Supply
Supply Current--Normal Mode Supply Current--Standby Mode Notes a. CSTRAY < 5 pF on COSC. After Start-Up, VDD of 3 V. b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. c. Guaranteed by design, not subject to production testing. No Load, VLL = 0 to VDD fOSC = 1 MHz, ROSC = 7.0 k ENABLE = Low VDD = 2.7 V VDD = 4.5 V 1.1 1.6 250 1.5 2.3 330 mA A
IDD
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TYPICAL CHARACTERISTICS (LL = VDD, 25C UNLESS OTHERWISE NOTED)
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SI9161
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TYPICAL CHARACTERISTICS (LL = VDD, 25C UNLESS OTHERWISE NOTED)
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PIN CONFIGURATIONS
PIN DESCRIPTION
Pin 1: VDD The positive power supply for all functional blocks except output driver. A bypass capacitor of 0.1 F (minimum) is recommended. Pin 2: LL A logic high on this pin allows normal operation. A logic low places the chip in light-load optimized-efficiency mode. In light-load mode, the oscillator frequency is reduced and DR goes high, disabling synchronous rectification. Do not leave pin unconnected. Pin 3: DMAX Used to set the maximum duty cycle. Pin 4: COMP This pin is the output of the error amplifier. A compensation network is connected from this pin to the FB pin to stabilize the system. This pin drives one input of the internal pulse width modulation comparator. Pin 5: FB The inverting input of the error amplifier. An external resistor divider is connected to this pin to set the regulated output voltage. The compensation network is also connected to this pin. Pin 6: NI The non-inverting input of the error amplifier. In normal operation it is externally connected to VREF or an external reference. Pin 7: VREF This pin supplies a 1.5-V reference. Pin 11: COSC An external capacitor is connected to this pin to set the normal oscillator frequency.
0.70 f OSC ----------------------------------R OSC x C OSC (at VDD = 5.0 V)
Pin 8: GND (Ground) Pin 9: ENABLE A logic high on this pin allows normal operation. A logic low places the chip in the standby mode. In standby mode, normal operation is disabled, supply current is reduced, the oscillator stops, and DS goes low while DR goes high. Pin 10: ROSC A resistor connected from this pin to ground sets the oscillator's capacitor (COSC) charge and discharge current. See the oscillator section of the description of operation.
Pin 12: UVLOSET This pin will place the chip in the standby mode if the UVLOSET voltage drops below 1.2 V. Once the UVLOSET voltage exceeds 1.2 V, the chip operates normally. There is a built-in hysteresis of 200 mV. Pin 13: PGND The negative return for the VS supply. Pin 14: DS This CMOS push-pull output pin drives the external n-channel MOSFET. This pin will be low in the standby mode. A breakbefore-make function between DS and DR is built-in.
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Pin 15: DR This CMOS push-pull output pin drives the external p-channel MOSFET. This pin will be high in the standby and light-load modes. A break-before-make function between the DS and DR is built-in. Pin 16: VS The positive terminal of the power supply which powers the CMOS output drivers. A bypass capacitor is required.
FUNCTIONAL BLOCK DIAGRAM
TIMING WAVEFORMS
Note: Timing waveforms are not to scale.
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OPERATION OF THE SI9161 BOOST CONVERTER
The SI9161 combined with optimized complementary MOSFETs provides the ideal solution to small, high efficiency, synchronous boost power conversion. Optimized for a 1-cell lithium ion, or 3-cell to 4-cell Nickel metal hydride battery, it is capable of switching at frequencies of up to 2 MHz. Combined with the Si6801, a complimentary high-frequency MOSFET, efficiencies of over 90% are easily achieved in a very small area; with light-load mode, efficiency over 80% can be achieved at power less than 1/2 W. PWM Controller The SI9161 implements a user-selectable synchronous/nonsynchronous voltage mode PWM control topology and is especially designed for battery power conversion. Voltagemode control results in the most efficient power conversion solution. Figure 1 below illustrates a schematic for a synchronous boost converter with an input range of 2.7 V to 5 V which covers the range of 1-cell LiIon and 3-cell or 4-cell NiMH/NiCd battery input respectively, and an output voltage of 5 V. Note the maximum input voltage is limited to the output voltage for a boost converter. The switching frequency is determined by an external capacitor and resistor connected to Cosc and Rosc pins. The graph on page 5 in the Typical Characteristics section shows the typical Cosc and Rosc values for various switching frequency. SI9161 oscillator frequency can be easily synchronized to external frequency as long as external switching frequency is higher than the internal oscillator frequency. The synchronization circuit is a series resistor and capacitor fed into the Cosc pin of the SI9161. The synchronization pulse should be greater than 1.5 V in amplitude and a near square wave pulsed clock. Figure 1 shows typical values for the synchronization components.
FIGURE 1. SI9161 Boost Converter
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Startup Designed to operate with single cell Lithium Ion battery voltage, the SI9161 has an operating range of 2.7 V to 6.0 V. During start-up, the device requires 3.0 V to guarantee proper operation, although it will typically start up at less than 2.2 V. Once powered, SI9161 will continue to operate until the voltage at VDD is 2.7 V; at this point, the battery is basically dead. During start-up, power for the chip is provided by the battery through R5 to VDD and through schottky diode D1 to VS pins. Once the converter is fully operating, VS supply power is provided by the converter output through diode D2, which overrides the D1 diode. This self perpetuating method of powering further improves the converter efficiency by utilizing higher gate drive to lower the on-resistance loss of the MOSFET. Another benefit of powering from the output voltage is it provides minimum load on the converter. This prevents the converter from skipping frequency pulses typically referred to as Burst or Pulse-Skipping modes. Pulse skipping mode could be dangerous, especially if it generates noise in RF, IF, or signal processing frequency bands. Enable and Under Voltage Shutdown The SI9161 is designed with programmable under-voltage lockout and enable features. These features give designers flexibility to customize the converter design. The undervoltage lockout threshold is 1.2 V. With a simple resistor divider from VDD, SI9161 can be programmed to turn-on at any VDD voltage. The ENABLE pin, a TTL logic compatible input, allows remote shutdown as needed. Gate Drive and MOSFETs The gate drive section is designed to drive the high-side p-channel switch and low-side n-channel switch. The internal 40 ns break-before-make (BBM) timing prevents both MOSFETs from turning-on simultaneously. The BBM circuit monitors both drive voltages, once the gate-to-source voltage drops below 2.5 V, the other gate drive is delayed 40-ns before it is allowed to drive the external MOSFET (see Figure 2 for timing diagram). This smart gate drive control provides additional assurance that shoot-through current will not occur.
FIGURE 2. Gate Drive Timing Diagrams The MOSFET used is the Si6801, an n- and p-channel in a single package TSSOP-8. The Si6801 is optimized to have very low gate charge and gate resistance. This results in a great reduction in gate switching power losses. The average time to switch on and off a MOSFET in a conventional structure is about 20 ns. The Si6801 will switch on and off in <5 ns, see Figure 3.
Note the Speed These MOSFETs have switching speeds of <5 ns. This high speed is due to the fast, high current output drive of the SI9161 and the optimized gate charge of the Si6801.
FIGURE 3. Gate Switching Times
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Stability Components A voltage mode boost converter is normally stabilized with simple lag compensation due to the additional 90 phase lag introduced by the additional right hand plane zero, as well as having a duty factor dependent resonant frequency for the output filter. The stability components shown in Figure 1 have been chosen to ensure stability under all battery conditions while maintaining maximum transient response. To do this we have used simple lag compensation (type 1 amplifier configuration). Figure 4 shows the bode plot for the above circuit, maintaining > 50 phase margin over the entire battery voltage range. The inductance value for the converter is a function of the desired ripple voltage and efficiency as stated below. In order to keep the ripple small and improve efficiency, the inductance needs to be large enough to maintain continuous current mode. Continuous current mode has lower RMS current compared to discontinuous current mode since the peak current is lower. This lowers the conduction loss and improves efficiency. The equation that shows the critical inductance which separates continuous and discontinuous current mode at any given output current is stated below. This equation is also plotted in Figure 5 as a function of input voltage.
V IN ( V OUT - V IN ) L = ------------------------------------------------------2 2 V OUT I OUT f = efficiency
2
FIGURE 4. Stability, with 1-cell Li battery input, 5 V @ 600-mA output. Energy Storage Components The input and output ripple voltage is determined by the switching frequency, and the inductor and capacitor values. The higher the frequency, inductance, or capacitance values, the lower the ripple. The efficiency of the converter is also improved with higher inductance by reducing the conduction loss in the switch, synchronous rectifier, and the inductor itself. In the past, Tantalum was the preferred material for the input and output capacitors. Now, with 2-MHz switching frequencies, Tantalum capacitors are being replaced with smaller surface mount ceramic capacitors. Ceramic capacitors have almost no equivalent series resistance (ESR). Tantalum capacitors have at least 0.1- ESR. By reducing ESR, converter efficiency is improved while decreasing the input and output ripple voltage. With ceramic capacitors, output ripple voltage is a function of capacitance only. The equation for determining output capacitance is stated below.
I OUT ( V OUT - V IN ) C = -------------------------------------------------V OUT V RIPPLE f IOUT VOUT VIN VRIPPLE f = = = = = output dc load current output voltage input voltage desired output ripple voltage switching frequency
FIGURE 5. Continous and Discontinous Inductance Curve Designed with small surface mount inductors and capacitors, the SI9161 solution can fit easily within a small space such as a battery pack. Another distinct advantage of a smaller converter size is that it reduces the noise generating area by reducing the high current path; therefore radiated and conducted noise is less likely to couple into sensitive circuits.
RESULTS SECTION
The following section shows the actual results obtained with the circuit diagram shown in Figure 1. Efficiency The graph below shows the efficiency of the above design at various constant switching frequencies. The frequencies were generated using a 3-V square wave of the desired frequency to the sync input to the circuit. The input voltage to the circuit is 3.6-V dc.
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FIGURE 6. Efficiency of SI9161 and Si6801 Boost converter at various fixed frequencies
FIGURE 7. Output noice of the Si9160 demo board
Output Noise The noise generated by a dc-dc converter is always an issue within the mobile phone. The SI9161 offers two benefits. 1. The noise spectrum is a constant, i.e. no random noise or random harmonic generation. 2. The switching fundamental can be synchronized to a known frequency, e.g. 812.5 kHz which is -th of the GSM/DCS system clock, or 1.23 MHz which is the channel spacing frequency for CDMA, etc.
Figures 7 through 9 show the output noise and output spectrum analysis. Output Noise Spectrum Note there is no random noise, only switching frequency harmonics. This is very good news for the RF stages, where an unknown, or random noise spectrum will cause problems.
FIGURE 8. Spectrum response for the SI9161 demo board output voltage
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FIGURE 9. Higher resolution of noise spectrum Conclusion Switching at high, known frequencies results in a smaller footprint while maintaining high efficiency. Efficiencies at high switching frequencies can be improved by using Si6801 optimized low gate charge and low gate resistance MOSFET. Even though the high frequency MOSFET has been designed with minimum gate charge, it still presents significant power loss during the light load conditions. In order to minimize this switching loss, SI9161 is designed with a light load efficiency improvement pin which decreases the switching frequency by 8.5 times (@ 1 MHz) and disables the synchronous rectification. This feature improves the light load efficiency in certain conditions as much as 50% compare to Si9160. Additionally, under transmitting mode, SI9161 clock frequency can be synchronized to higher external frequency which eliminates or greatly reduces any radio interference concerns and pushes harmonics out beyond signal processing frequencies.
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